Semiconductor device

ABSTRACT

A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority from Japanese patentapplication JP 2003-162139 filed on Jun. 6, 2003, the content of whichis hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor device, and moreparticularly to a technique which is effectively applicable to asemiconductor device which connects bonding pads of a semiconductor chipand connecting portions which are arranged around the semiconductor chipusing bonding wires.

[0003] With respect to semiconductor devices, semiconductor deviceshaving various package structures which differ depending on functionsand kinds of integrated circuits mounted on a semiconductor chip havebeen commercialized. As one of these semiconductor devices, there hasbeen known a semiconductor device which is referred to as a QFP (QuadFlatpack Package) type semiconductor device. The QFP type semiconductordevice is mainly constituted of a semiconductor chip having a mainsurface on which a plurality of bonding pads and a plurality of buffercells are arranged, a plurality of leads arranged around thesemiconductor chip, a plurality of bonding wires which electricallyconnect the plurality of the bonding wires of the semiconductor chip andthe plurality of leads respectively, support bodies (tabs, die pads)provided for supporting the semiconductor chips, suspending leads whichare integrally formed with the support bodies, and a sealing body whichseals the semiconductor chip, the plurality of bonding wires, and innerlead portions of the plurality of leads.

[0004] The plurality of bonding pads include a plurality of signalbonding pads and a plurality of power source bonding pads and arearranged along respective sides of the semiconductor chip. The pluralityof buffer cells include a plurality of input-output cells (I/O cells)and a plurality of power source cells, wherein the plurality ofinput-output cells are arranged corresponding to the plurality ofrespective signal bonding pads and the plurality of power source cellsare arranged corresponding to the plurality of respective power sourcebonding pads. The plurality of leads include a plurality of signal leadsand a plurality of power source leads, wherein the plurality of signalleads are arranged corresponding to the plurality of respective signalbonding pads and the plurality of power source leads are arrangedcorresponding to the plurality of respective power source bonding pads.

[0005] Here, a technique for respectively electrically connecting theplurality of bonding pads of the semiconductor chip with the pluralityof leads arranged around the semiconductor chip is described in JapaneseUnexamined Patent Publication Hei 6(1994)-283604, for example.

[0006] [Patent Reference 1]

[0007] Japanese Unexamined Patent Publication Hei 6(1994)-283604

SUMMARY OF THE INVENTION

[0008] Here, the number of bonding pads of the semiconductor chip issteadily increasing along with a demand for higher packaging andmulti-functioning of integrated circuits which are mounted on thesemiconductor chip. The number of leads is increased along with theincrease of the bonding pads and hence, a profile size of thesemiconductor device is increased. Accordingly, efforts have been madeto miniaturize the semiconductor device by narrowing an arrangementpitch of leads by minimizing a size of leads. With respect to a recentQFP type semiconductor device, the arrangement pitch is narrowed to alevel of 0.3 [mm] to 0.4 [mm]. However, a given bonding area isnecessary to ensure the reliability at the time of mounting thesemiconductor device on a printed wiring circuit board by soldering anda mechanical strength is necessary to some extent to suppress bending ofthe leads. Accordingly, it is considered that further miniaturization ofthe semiconductor device by the further minimization of the size ofleads is difficult.

[0009] In view of the above, the inventors of the present invention havefocused their attention on a fact that a plurality of power sourcebonding pads and a plurality of power source leads are provided for oneoperational potential (for example, Vcc=3.3[V]) to ensure the stableoperation of integrated circuits mounted on a semiconductor chip andhave made the present invention.

[0010] It is an object of the present invention to provide a techniquewhich can miniaturize a semiconductor device.

[0011] The abovementioned and further objects and novel features of thepresent invention will become apparent by the description of thisspecification and attached drawings.

[0012] To briefly explain the summary of representative inventionsdisclosed in this specification, they are as follows.

[0013] That is, bonding pads having the same function which are arrangedon a main surface of a semiconductor chip are electrically connected toeach other using bonding wires. For example, the semiconductor devicehas a following constitution.

[0014] The semiconductor device includes a semiconductor chip, aplurality of bonding pads which are formed on a main surface of thesemiconductor chip and include first power source bonding pads, secondpower source bonding pads and a plurality of signal bonding pads, aplurality of leads which are arranged around the semiconductor chip andinclude first power source leads and a plurality of signal leads, aplurality of bonding wires which include first bonding wires forconnecting the first power source bonding pads with the first powersource leads, second bonding wires for connecting the first bonding padswith second bonding pads and the plurality of third bonding wires forconnecting the plurality of signal bonding pads with the plurality ofsignal leads, and a sealing body which seals the semiconductor chip, theplurality of bonding wires and some of the plurality of leads.

[0015] According to the abovementioned means, it is possible to reducethe number of power source leads which are electrically connected tosecond power source leads via the bonding wires and hence, thesemiconductor device can be miniaturized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1(a) and FIG. 1(b) are views showing the inner structure of asemiconductor device according to an embodiment 1 of the presentinvention, wherein FIG. 1(a) is a schematic plan view and FIG. 1(b) is aschematic cross-sectional view;

[0017]FIG. 2(a) and FIG. 2(b) are views showing the inner structure ofthe semiconductor device according to the embodiment 1 of the presentinvention, wherein FIG. 2(a) is a schematic cross-sectional view alongthe signal lead and FIG. 2(b) is a schematic cross-sectional view alongpower source leads;

[0018]FIG. 3 is schematic plan view which enlarges a portion of FIG.1(a);

[0019]FIG. 4 is schematic plan view which enlarges a portion of FIG. 3;

[0020]FIG. 5 is schematic plan view which enlarges a portion of FIG. 3;

[0021]FIG. 6 is a schematic cross-sectional view showing the connectionstate of the bonding wires in FIG. 5;

[0022]FIG. 7 is a planar layout view of a semiconductor chip shown inFIG. 1(a);

[0023]FIG. 8 is a planar layout view which enlarges a portion of FIG. 7;

[0024]FIG. 9 is a planar layout view which enlarges a portion of FIG. 7;

[0025]FIG. 10 is a planar layout view which enlarges a portion of FIG.7;

[0026]FIG. 11 is a schematic cross-sectional view showing the innerstructure of the semiconductor chip shown in FIG. 7;

[0027]FIG. 12(a) and FIG. 12(b) are views showing the inner structure ofthe semiconductor device according to a modification of the embodiment 1of the present invention, wherein FIG. 12(a) is a schematiccross-sectional view along the signal lead and FIG. 12(b) is a schematiccross-sectional view along power source leads;

[0028]FIG. 13(a) and FIG. 13(b) are views showing the inner structure ofthe semiconductor device according to a modification of the embodiment 2of the present invention, wherein FIG. 13(a) is a schematiccross-sectional view along the signal lead and FIG. 13(b) is a schematiccross-sectional view along power source leads;

[0029]FIG. 14 is a planar layout view of some of semiconductor chipsmounted on the semiconductor device which is a modification 3 of theembodiment 1 of the present invention;

[0030]FIG. 15(a) and FIG. 15(b) are views showing the inner structure ofa semiconductor device according to an embodiment 2 of the presentinvention, wherein FIG. 15(a) is a schematic plan view and FIG. 15(b) isa schematic cross-sectional view;

[0031]FIG. 16(a) and FIG. 16(b) are views showing the inner structure ofthe semiconductor device according to the embodiment 2 of the presentinvention, wherein FIG. 16(a) is a schematic cross-sectional view alongthe signal lead and FIG. 16(b) is a schematic cross-sectional view alongpower source leads;

[0032]FIG. 17 is a schematic plan view showing a portion of FIG. 15(a)in an enlarged manner;

[0033]FIG. 18 is a schematic plan view showing a portion of FIG. 17 inan enlarged manner;

[0034]FIG. 19 is a schematic plan view showing a portion of FIG. 17 inan enlarged manner;

[0035]FIG. 20 is a planar layout view of a semiconductor chip shown inFIG. 15(a);

[0036]FIG. 21 is a planar layout view showing a portion of FIG. 20 in anenlarged manner;

[0037]FIG. 22 is a schematic cross-sectional view showing the innerstructure of the semiconductor chip in FIG. 20,

[0038]FIG. 23(a) and FIG. 23(b) are views showing the inner structure ofa semiconductor device according to an embodiment 3 of the presentinvention, wherein FIG. 23(a) is a schematic plan view and FIG. 23(b) isa schematic cross-sectional view;

[0039]FIG. 24(a) and FIG. 24(b) are views showing the inner structure ofa semiconductor device according to an embodiment 4 of the presentinvention, wherein FIG. 24(a) is a schematic plan view and FIG. 24(b) isa schematic cross-sectional view;

[0040]FIG. 25(a) and FIG. 25(b) are views showing the inner structure ofa semiconductor device according to an embodiment 5 of the presentinvention, wherein FIG. 25(a) is a schematic plan view and FIG. 25(b) isa schematic cross-sectional view;

[0041]FIG. 26(a) and FIG. 26(b) are views showing the inner structure ofa semiconductor device according to an embodiment 6 of the presentinvention, wherein FIG. 26(a) is a schematic plan view and FIG. 26(b) isa schematic cross-sectional view;

[0042]FIG. 27 is a schematic plan view showing the inner structure of asemiconductor device according to an embodiment 7 of the presentinvention;

[0043]FIG. 28 is a schematic plan view of a portion of FIG. 27 in anenlarged manner;

[0044]FIG. 29 is a planar layout view of a semiconductor chip shown inFIG. 27;

[0045]FIG. 30 is a plan view of a semiconductor wafer used in themanufacture of the semiconductor device of the embodiment 7 of thepresent invention;

[0046]FIG. 31 is a view for explaining a characteristics inspection stepin the manufacture of the semiconductor device in the embodiment 7;

[0047]FIG. 32 is a schematic plan view showing the inner structure ofthe semiconductor device according to an embodiment 8 of the presentinvention;

[0048]FIG. 33(a) to FIG. 33(c) are views showing a profile of thesemiconductor device for explaining advantageous effects of the presentinvention more specifically, wherein FIG. 33(a) is a standard profileview and FIG. 33(b) and FIG. 338(c) are profile views to which thepresent invention is applied;

[0049]FIG. 34(a) and FIG. 34(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 1 ofthe present invention, wherein FIG. 34(a) is a schematic plan view andFIG. 34(b) is a schematic cross-sectional view;

[0050]FIG. 35(a) and FIG. 35(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 4 ofthe present invention, wherein FIG. 35(a) is a schematic plan view andFIG. 35(b) is a schematic cross-sectional view;

[0051]FIG. 36(a) and FIG. 36(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 6 ofthe present invention, wherein FIG. 36(a) is a schematic plan view andFIG. 36(b) is a schematic cross-sectional view;

[0052]FIG. 37(a) and FIG. 37(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 6 ofthe present invention, wherein FIG. 36(a) is a schematic plan view andFIG. 36(b) is a schematic cross-sectional view;

[0053]FIG. 38(a) and FIG. 38(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 6 ofthe present invention, wherein FIG. 36(a) is a schematic plan view andFIG. 36(b) is a schematic cross-sectional view;

[0054]FIG. 39(a) and FIG. 39(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 7 ofthe present invention, wherein FIG. 36(a) is a schematic plan view andFIG. 36(b) is a schematic cross-sectional view;

[0055]FIG. 40(a) and FIG. 40(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 1 ofthe present invention, wherein FIG. 40(a) is a schematic plan view andFIG. 40(b) is a schematic cross-sectional view;

[0056]FIG. 41(a) and FIG. 41(b) are views showing the inner structure ofa semiconductor device according to a modification of an embodiment 7 ofthe present invention, wherein FIG. 41(a) is a schematic plan view andFIG. 41(b) is a schematic cross-sectional view;

[0057]FIG. 42 is a schematic plan view showing the inner structure ofthe semiconductor device according to the embodiment 9 of the presentinvention; and

[0058]FIG. 43 is a schematic circuit diagram view showing the innerstructure of the semiconductor device according to the embodiment 9 ofthe present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] Preferred embodiments of the present invention are described indetail in conjunction with attached drawings hereinafter. In alldrawings that are served for explaining the embodiments, the samesymbols are given to identical parts and their repeated explanation isomitted.

[0060] (Embodiment 1)

[0061] In this embodiment 1, the explanation is made with respect to anexample in which the present invention is applied to a QFP (QuadFlatpack Package) type semiconductor device.

[0062]FIG. 1(a) and FIG. 1(b) are views showing the inner structure of asemiconductor device according to an embodiment 1 of the presentinvention, wherein FIG. 1(a) is schematic plan view and FIG. 1(b) is aschematic cross-sectional view.

[0063]FIG. 2(a) and FIG. 2(b) are views showing the inner structure ofthe semiconductor device according to the embodiment 1 of the presentinvention, wherein FIG. 2(a) is a schematic cross-sectional view alongthe signal lead and FIG. 2(b) is a schematic cross-sectional view alongpower source leads.

[0064]FIG. 3 is schematic plan view which enlarges a portion of FIG.1(a);

[0065]FIG. 4 is schematic plan view which enlarges a portion of FIG. 3.

[0066]FIG. 5 is schematic plan view which enlarges a portion of FIG. 3.

[0067]FIG. 6 is a schematic cross-sectional view showing the connectionstate of the bonding wires in FIG. 5.

[0068]FIG. 7 is a planar layout view of a semiconductor chip shown inFIG. 1(a).

[0069]FIG. 8 is a planar layout view which enlarges a portion of FIG. 7.

[0070]FIG. 9 is a planar layout view which enlarges a portion of FIG. 7.

[0071]FIG. 10 is a planar layout view which enlarges a portion of FIG.7.

[0072]FIG. 11 is a schematic cross-sectional view showing the innerstructure of the semiconductor chip shown in FIG. 7.

[0073] As shown in FIG. 1 to FIG. 3, the semiconductor device of thisembodiment 1 is mainly constituted of a semiconductor chip 2, aplurality of leads 5, a plurality of bonding wires 8, a sealing body 9and the like. The semiconductor chip 2 is fixed by adhesion to a supportbody 6 which is referred to as a tab or a die pad, while, for example,four suspension leads 7 are integrally connected to the support body 6.

[0074] As shown in FIG. 7, a planar shape of the semiconductor chip 2along a thickness direction thereof is formed in a quadrangular shape.In this embodiment 1, for example, the planar shape of the semiconductorchip 2 is formed in a square shape having a size of 7.6 [mm]×7.6 [mm].

[0075] Although the semiconductor chip 2 is not limited to the followingconstitution, as shown in FIG. 11, the semiconductor chip 2 includesmainly a semiconductor board 20 and, on a main surface of thesemiconductor board 20, a multilayered wiring layer 22 which is formedby stacking insulation layers 22 a and wiring layers 22 b in a pluralityof stages and a surface protective film (a final protective film) 23which covers the multilayered wiring layer 22.

[0076] The insulation layers 23 a are formed of a silicon oxide film,for example. The wiring layers 22 b are formed of a metal film made of,for example, aluminum (Al), aluminum alloy, copper, copper alloy and thelike. The surface protective film 23 is formed of a multilayered filmwhich is formed by stacking an inorganic insulation film such as asilicon oxide film, a silicon nitride film and the like and an organicfilm. The semiconductor chip 2 of this embodiment 1 has, for example,the seven-layered metal wiring structure.

[0077] For example, a microcomputer which constitutes an integratedcircuit is mounted on the semiconductor chip 2. As shown in FIG. 7, on amain surface 2 x of the semiconductor chip 2, an internal circuitforming portion 10 is arranged. In the internal circuit forming portion10, an internal circuit including a plurality of circuit blocks 12 whichare divided by wiring channel regions are arranged. The plurality ofcircuit blocks 12 include, for example, the circuit block in which a CPU(Central Processing Unit) is formed as an arithmetic computing circuit,the circuit block in which a RAM (Random Access Memory) is formed as astorage circuit, the circuit block in which a ROM (Read Only Memory) isformed as a storage circuit, the circuit block in which a timer isformed, and the circuit block in which an IF (Serial CommunicationInterface Circuit) is formed.

[0078] On the main surface 2 x of the semiconductor chip 2, fourinterface circuit forming portions 11 are arranged corresponding torespective sides of the semiconductor chip 2. The four interface circuitforming portions 11 are arranged to surround the internal circuitforming portion 10 in plane.

[0079] In each interface circuit forming portion 11, as shown in FIG. 7and FIG. 8, an interface circuit which includes a plurality of bondingpads 3 and a plurality of buffer cells 4 is arranged. The plurality ofbonding pads 3 include a plurality of signal bonding pads 3 a and aplurality of power source bonding pads 3 b, while the plurality ofbuffer cells 4 include a plurality of input/output cells (I/O cells) 4 aand a plurality of power source cells 4 b.

[0080] In each of the interface circuit forming portions 11, theplurality of bonding pads 3 and the plurality of buffer cells 4 arearranged along sides of the semiconductor chip 2. The plurality ofbonding pads 3 are arranged between the sides of the semiconductor chip2 and the plurality of buffer cells 4, wherein the plurality ofinput/output cells 4 a are arranged corresponding to the plurality ofsignal bonding pads 3 a and the plurality of the power source cells 4 bare arranged corresponding to the plurality of power source bonding pads3 b.

[0081] As shown in FIG. 9, on the interface circuit forming portions 11,a power source line 14 which supplies an operational potential to theplurality of input/output cells 4 a is arranged. The power source line14 is continuously extended in a ring-like shape such that the powersource line 14 surrounds the internal circuit forming portion 10 inplane.

[0082] The signal bonding pads 3 a are electrically connected with thecorresponding input/output cells 4 a, while the power source bondingpads 3 b are electrically connected with the corresponding power sourcecells 4 b. Further, the plurality of power source cells 4 b areelectrically connected with the power source line 14, while the powersource line 14 is electrically connected with the plurality ofinput/output cells 4 a.

[0083] The input/output cells 4 a are cells which include circuits fortransmitting and receiving input/output signals, while the power sourcecells 4 b are cells for supplying the operational potential necessaryfor the circuit operation of the input/output cells 4 a.

[0084] For operating the plurality of the input/output cells 4 a in astable manner, the plurality of power source bonding pads 3 b are, asshown in FIG. 8 and FIG. 9, arranged to sandwich the plurality of signalbonding pads 3 a in plane.

[0085] As a transistor element which constitutes the internal circuitand the interface circuit, for example, a MISFET (Metal InsulatorSemiconductor Field Effect Transistor) is used. Aiming at the low powerconsumption and the rapid processing, the arithmetic computing circuitof the internal circuit uses the MISFET which is operated with theoperational potential lower than an operational potential for operatingthe MISFET which constitutes the buffer cells 4 of the interfacecircuit. For example, the arithmetic computing circuit of the internalcircuit uses the MISFET which is operated with the operational potentialof 1.8[V], while buffer cell 4 of the interface circuit uses the MISFETwhich is operated with the operational potential of 3.3[V].

[0086] As shown in FIG. 10, the signal bonding pads 3 a and the powersource bonding pads 3 b have respective planar surfaces thereof formedin a quadrangular shape. In the embodiment 1, the signal bonding pad 3 ais formed in a square shape having a size of 0.1 [mm]×0.1 [mm], forexample, while the power source bonding pad 3 b is formed in arectangular shape having a size of 0.1 [mm]×0.2 [mm], for example. Thepower source bonding pads 3 b are arranged along the direction which isequal to the direction that longitudinal sides of the power sourcebonding pads 3 b are away from the sides 2 a of the semiconductor chip2.

[0087] As shown in FIG. 1 and FIG. 2, the semiconductor chip 2, some ofthe plurality of leads 5, the support body 6, four suspending leads 7,the plurality of bonding wires 8 and the like are sealed by the sealingbody 9. The sealing body 9 has a planar shape thereof along a thicknessdirection thereof formed in a quadrangular shape. In this embodiment 1,the planar shape of the sealing body 9 is formed in a square shapehaving a size of 16 [mm]×16 [mm], for example.

[0088] For reducing stress in the sealing body 9, the sealing body 9 isformed of, for example, a biphenyl-based thermosetting resin to which aphenol-based curing agent, silicone rubber, filler and the like areadded. Further, the sealing body 9 is formed by a transfer moldingmethod which is suitable for mass production. The transfer moldingmethod is a technique which uses a forming mold having a pot, runners,resin injection gates, a cavity and the like and forms a sealing body byinjecting thermosetting resin such as epoxy resin, for example, into thecavity from the pot through the runners and the resin injection gates.

[0089] The plurality of leads 5 are, as shown in FIG. 1 to FIG. 3,arranged around the semiconductor chip 2 such that the leads 5 surroundthe semiconductor chip 2 in plane. Further, the plurality of leads 5 arearranged along the respective sides of the sealing body 9.

[0090] The plurality of leads 5 extend over the inside and the outsideof the sealing body 9 and are constituted of inner lead portions (innerleads) which are positioned inside the sealing body 9 and the outer leadportions (outer leads) which are positioned outside the sealing body 9.

[0091] The inner lead portions of the plurality of leads 5 extend fromthe side surfaces of the sealing body 9 to the side surfaces of thesemiconductor chip 2 and respective distal end portions thereof areprovided with connecting portions to which the bonding wires 8 areconnected.

[0092] The outer lead portions of the plurality of leads 5 are molded ina gull wing shape which constitutes one of surface mounting type leadshapes. The outer lead portions molded in a gull wing shape includefirst portions which project from the side surfaces of the sealing body9 and second portions which are bent downwardly (a back surface side outof a main surface and a back surface of the sealing body 9 which arepositioned at sides opposite from each other) from the first portions,and third portions which extend in the same direction as the projectingdirection of the first portions from the second portions. The thirdportions of the outer lead portions are used as external connectionterminals at the time of mounting the semiconductor device on theprinted wiring circuit board by soldering.

[0093] As shown in FIG. 2 to FIG. 5, the plurality of leads 5 includethe plurality of signal leads 5 a and, further, include one power sourcelead 5 b to which the operational potential Vcc of 3.3[V], for example,is applied. The plurality of bonding wires 8 include a plurality ofbonding wires 8 a which respectively electrically connect the pluralityof signal bonding pads 3 a of the semiconductor chip 2 with theplurality of signal leads 5 a. The plurality of bonding wires 8 furtherinclude a bonding wire 8 b which electrically connects an arbitrarypower source bonding pad 3 b out of the plurality of power sourcebonding pads 3 b of the semiconductor chip 2 with the power source lead5 b. The plurality of bonding wires 8 still further include a pluralityof bonding wires 8 c which electrically connect the power source bondingpads 3 b of the semiconductor chip 2 having the same function to eachother.

[0094] As shown in FIG. 4 and FIG. 5, out of the plurality of powersource bonding pads 3 b, an arbitrary power source bonding pad 3 b iselectrically connected with the power source lead 5 b via the bondingwire 8 b. The electric connection is established between the respectivepower source bonding pads 3 b including the arbitrary power sourcebonding pad 3 b using the bonding wire 8 c. That is, the arbitrary powersource bonding pad 3 b which is electrically connected with the powersource lead 5 b to which the operational potential Vcc is applied viathe bonding wire 8 b is connected to the plurality of power sourcebonding pads 3 b except for the arbitrary power source bonding pad 3 busing the bonding wire 8 c. Due to such a constitution, it is possibleto reduce the number of power source leads 5 b by an amountcorresponding to the number of power source bonding pads 3 b which areelectrically connected with the arbitrary power source bonding pads 3 bvia the bonding wire 8 c and hence, the semiconductor device can beminiaturized. In the embodiment 1, for example, while 24 power sourcebonding pads 3 b are provided, one power source lead 5 b is connectedwith one of the power source bonding pads 3 b via the bonding wire 8 band hence, 23 power source leads 5 b can be reduced.

[0095] The superiority of the present invention is further explained inconjunction with FIG. 33. As shown in FIG. 33(a), when the semiconductorchip is packaged in the conventional manner, the package has a profilesize which is 20 mm×20 mm and the number of lead pins becomes 144(hereinafter the package being expressed as 2020-144pin). However, asshown in FIG. 33(b), when the constitution described in the embodiment 1is applied to the bonding pads for reference potential (Vss: 0V, forexample), the package becomes 1616-120pin and hence, a package area canbe reduced to 64% of the conventional structure. Here, in addition tothe abovementioned bonding pads for reference potential (Vss), theconstitution described in the embodiment 1 may be applied to the bondingpads for power source potential (Vcc: 3.3V, for example). In this case,as shown in FIG. 33(c), the package becomes 1414-100pin and hence, apackage area can be reduced to 49% of the conventional structure. Here,in FIG. 33(a), FIG. 33(b) and FIG. 33(c), to enable a viewer to graspthe package size shrinking effect more visually, the respective packagesare depicted at ratios provided that the package 2020-144pin shown inFIG. 33(a) assumes the size of 100%.

[0096] Further, in the application of the present invention to thesemiconductor device, when the package size is not reduced, it ispossible to widen the pitch of the outer leads. Accordingly, narrowingof the pitch of the printed wiring circuit board for mounting thepackages can be alleviated and hence, mounting of the semiconductordevice on the printed wiring circuit board is facilitated. Further,since a width between the outer leads can be increased, the reliabilityafter soldering is enhanced.

[0097] As the bonding wires 8, gold (Au) wires are used. Gold exhibitsthe low specific resistance compared to Al or Cu which is generally usedas a wiring material of the semiconductor chip 2. Further, a diameter ofthe bonding wire is approximately several tens micron which is arelatively large value, while a thickness of the wiring of thesemiconductor chip 2 is reduced to several micron to several hundredsmicron. Accordingly, there exists a tendency that the sheet resistanceof the bonding wires is considerably lower than the sheet resistance ofthe wiring of the semiconductor chip 2. That is, the electric resistanceof the bonding wires 8 is lower than the electric resistance of thepower source line 14. In this manner, by connecting the arbitrary powersource bonding pad 3 b with the power source lead 5 b using the Au wireand by connecting between the respective power source bonding pads 3 bincluding the arbitrary power source bonding pad 3 b using the Au wire,it is possible to uniformly supply the operational potential to therespective power source bonding pads 3 b without generating the largepotential difference.

[0098] As shown in FIG. 4 and FIG. 5, the plurality of bonding pads 3which include the plurality of signal bonding pads 3 a and the pluralityof power source bonding pads 3 b are arranged along the respective sidesof the semiconductor chip 2 such that these bonding pads 3 surround theinternal circuit forming portion 10 in plane. On the other hand, thebonding wire 8 c connects the power source bonding pads 3 b to eachother, wherein the power source bonding pads 3 b sandwich a given numberof signal bonding pads 3 a therebetween. That is, at respective sides ofthe semiconductor chip 2, the bonding wire 8 c which connects betweenthe power source bonding pads 3 b extends along the sides of thesemiconductor chip 2.

[0099] In connecting the power source bonding pads 3 b to each other bythe bonding wire 8 c in this manner, in order to avoid a contact betweenthe bonding wires 8 a connected to the signal bonding pads 3 a and thebonding wire 8 c, it is necessary to perform the connection between thepower source bonding pads 3 b and the bonding wire 8 c at a positionremoter from the side of the semiconductor chip 2 than the connectionbetween the signal bonding pads 3 a and the bonding wires 8 a. To putsuch a connection mode into practice, as shown in FIG. 10, it iseffective to form the power source bonding pad 3 b in a rectangularshape and to arrange the power source bonding pad 3 b such that longsides thereof are positioned away from the sides of the semiconductorchip 2. However, as a length of the long side of the power sourcebonding pads 3 b, it is necessary to ensure a length which prevents thebonding wire 8 b from interfering with the bonding wires 8 a. It ispreferable that the length of the long sides of the power source bondingpads 3 b is twice or more times greater than a length of the sides ofthe signal bonding pads 3 a which extend along the same direction as thelong sides of the power source bonding pads 3 b or is twice or moretimes greater than a length of the short sides of the signal bondingpads 3 a.

[0100] By forming the power source bonding pad 3 b in such a rectangularshape, it is possible to make the power source bonding pads 3 bconnected to each other using the bonding wire 8 c while preventing thepower source bonding pads 3 b from coming into contact with the bondingwire 8 a connected to the signal bonding pad 3 a.

[0101] Here, the size and the shape of the power source bonding pad maybe sufficient when two bonding wires can be connected to the powersource bonding pad basically. For example, when the number of thebonding pads is small compared to the size of the semiconductor chip andthere exists a tolerance with respect to a pad interval, for example,the power source bonding pads at both sides may be set to a length whichcan prevent the bonding wire 8 b from interfering with the bonding wire8 a. In this case, although the number of the bonding pads of thesemiconductor chip is decreased compared to the above-mentioned exampleof the longitudinal bonding pads, the connection region of the bondingpad to which the bonding wires are connected is increased and hence, itis possible to sufficiently ensure the margin of accuracy with respectto the size or a landing point of the capillary.

[0102] The bonding wires 8 a are, as shown in FIG. 2(a), connected by anail head bonding (ball bonding) method which performs the primaryconnection at the signal bonding pads 3 a of the semiconductor chip 2and performs the secondary connection at the connecting portions of thesignal leads 5. The nail head bonding method performs the primaryconnection by forming balls on distal end portions of the wires and,thereafter, by bonding the balls to the first connecting portions usingthermal compression bonding processing and, thereafter, performs thesecondary connection by pulling around the wires to the secondconnecting portions and, thereafter, the wires are connected to thesecond connecting portions while applying the ultrasonic vibrations.

[0103] On the other hand, the bonding wire 8 b is, as shown in FIG.2(b), connected by a reverse nail head bonding method which performs theprimary connection at the power source lead 5 b and performs thesecondary connection at the arbitrary power source bonding pad 3 b ofthe semiconductor chip 2. In this manner, by performing the wireconnection of the power source lead 5 b and the power source bonding pad3 b using the reverse nail head bonding method, a height of the bondingwire 8 b on the power source bonding pad 3 b can be lowered and hence, adistance between the capillary and the bonding pad 3 b at the time ofconnecting the bonding wire 8 c to the bonding pad 3 b can be widened.As a result, compared to a case that the wire connection of the powersource bonding pad 3 b with the power source lead 5 b is performed by anail head bonding method similar to the nail head bonding method usedfor the signal bonding wires 8 a shown in FIG. 2(a), an area of thepower source bonding pad can be reduced.

[0104] The plurality of power source bonding pads 3 b are, as shown inFIG. 4 and FIG. 5, connected in series by the bonding wire 8 c using thearbitrary power source bonding pad 3 b to which the bonding wire 8 b isconnected as a starting point. When the plurality of power sourcebonding pads 3 b are connected in series, two bonding wires 8 c areconnected to other power source bonding pads 3 b except for the powersource bonding pad 3 b of an initial stage and the power source bondingpad 3 b of a final stage. In this embodiment 1, as shown in FIG. 6, theconnection is performed continuously as follows. A primary side of thebonding wire 8 c of the first stage is connected to the power sourcebonding pad 3 b of the first stage (initial stage). A secondary side ofthe bonding wire 8 c of the first stage is connected to the power sourcebonding pad 3 b of the second stage. A primary side of the bonding wire8 c of the second stage is connected to the power source bonding pad 3 bof the second stage via the secondary side of the bonding wire 8 c ofthe first stage. Thereafter, a secondary side of the bonding wire 8 c ofthe second stage is connected to the power source bonding pad 3 b of thethird stage. In this manner, when the plurality of power source bondingpads 3 b are connected in series by connecting two bonding wires 8 c toone bonding pad 3 b using a nail head bonding method, it is possible toreduce the area of the bonding pad 3 b by connecting the bonding wire 8c of the rear stage to the power source bonding pad 3 b in an overlappedmanner by way of the secondary side of the bonding wire 8 c of the frontstage.

[0105] Further, the power source bonding pad 3 b may be formed in alaterally elongated rectangular shape having long sides thereof extendedalong the side of the semiconductor chip 2. In this case, the number ofterminals of the semiconductor chip is reduced compared to the exampleof the above-mentioned longitudinal power source bonding pad 3 b.However, due to the application of this embodiment, more leads of thewhole package can be reduced compared to an amount of reduction of thenumber of terminals of the semiconductor chip.

[0106]FIG. 12(a) and FIG. 12(b) are views showing the inner structure ofthe semiconductor device according to a modification 1 of the embodiment1 of the present invention, wherein FIG. 12(a) is a schematiccross-sectional view along signal lead and FIG. 12(b) is a schematiccross-sectional view along power source lead.

[0107] In the abovementioned embodiment 1, as shown in FIG. 2(a), theexplanation is made with respect to the example in which the signalbonding pads 3 a and the signal leads 5 a are connected using thebonding wires 8 a by the nail head bonding method which performs theprimary connection at the signal bonding pads 3 a of the semiconductorchip 2 and the secondary connection at the connecting portion of thesignal leads 5 a. However, as shown in FIG. 12(a), the signal bondingpads 3 a of the semiconductor chip 2 and the connecting portions of thesignal leads 5 a may be connected using the bonding wires 8 a by a nailhead bonding method which performs the primary connection at the signalleads 5 a and the secondary connection at the signal bonding pads 3 a ofthe semiconductor chip 2. In this manner, by inversely bonding thebonding wires 8 a, a height of the bonding wires 8 a above the bondingpads 8 a is lowered and hence, a distance between the bonding wire 8 cand the bonding wires 8 a which extend along the arrangement directionof the bonding pads 3 is broadened whereby, when the sealing body 9 isformed by a transfer molding method, it is possible to suppress adrawback that both bonding wires (8 c, 8 a) are brought into contactwith each other due to the flowing-away of wires at the time ofinjecting resin.

[0108]FIG. 13(a) and FIG. 13(b) are views showing the inner structure ofthe semiconductor device according to a modification 2 of the embodiment1 of the present invention, wherein FIG. 13(a) is a schematiccross-sectional view along the signal lead and FIG. 13(b) is a schematiccross-sectional view along power source lead.

[0109] In the abovementioned modification 1, as shown in FIG. 12(a),another end side (secondary side) of the bonding wire 8 a is directlyconnected to the signal bonding pad 3 a of the semiconductor chip 2.However, as shown in FIG. 13(a), a projection electrode 16 may be formedon the signal bonding pad 3 a of the semiconductor chip 2 and theprojection electrode 16 may be connected to another side of the bondingwire 8 a. The projection electrode 16 may preferably be a stud bumpwhich is formed by a nail head bonding method, for example.

[0110] Further, as shown in FIG. 13(b), out of the plurality of powersource bonding pads 3 b, a projection electrode 16 may be formed in afirst region of the power source bonding pad 3 b which is electricallyconnected with the bonding wire 8 b via the lead 5, and another side(secondary side) of the bonding wire 8 b may be connected to theprojection electrode 16.

[0111] When the bonding pad side is set as the secondary side, since thecompression bonding method is adopted as the adhesion method, theadhesion strength cannot be ensured and, further, since the bonding padand the capillary come close to each other at the time of performing thecompression bonding, there exists a possibility that damages to thebonding pad is increased. On the other hand, by adopting the stud bumpmethod, it is possible to reduce damages to the Al pads of the chip and,at the same time, the adhesion strength can be ensured.

[0112]FIG. 14 is a planar layout view of some of semiconductor chipsmounted on the semiconductor device which is a modification 3 of theembodiment 1 of the present invention.

[0113] As shown in FIG. 14, the plurality of buffer cells 4 include theplurality of power source cells 4 b 1 and the plurality of bonding pads3 include the plurality of power source bonding pads 3 b 1. Theplurality of power source cells 4 b 1 are arranged corresponding to theplurality of power source bonding pads 3 b 1.

[0114] Between the interface circuit forming portions 11 and theinternal circuit forming portion 10, a power source line 15 forsupplying an operational potential (for example, 1.8V=Vdd) to theinternal circuit of the internal circuit forming portion 10, forexample, is arranged. The power source line 15 continuously extends in aring shape such that the power source line 15 surrounds the internalcircuit forming portion 10 in plane.

[0115] The power source bonding pads 3 b 1 are electrically connectedwith the corresponding power source cells 4 b 1. Further, the pluralityof power source cells 4 b 1 are electrically connected with the powersource line 15, while the power source line 15 is electrically connectedwith the internal circuit. The power source cells 4 b 1 are cells servedfor supplying an operational potential necessary for the circuitoperation of the internal circuit.

[0116] The plurality of power source bonding pads 3 b 1 are arrangedsuch that the power source bonding pads 3 b 1 sandwich the plurality ofsignal bonding pads 3 a in plane for enabling the internal circuit toperform the stable operation.

[0117] In the previously-mentioned embodiment 1, the explanation is madewith respect to the example in which the present invention is applied tothe plurality of power source pads 3 b which supply the operationalpotential Vcc to the input/output cells 4 a. However, as in the case ofthis modification 3, the present invention may be applicable to theplurality of power source bonding pads 3 b 1 which supply theoperational potential Vdd to the internal circuit. Also in this case,the number of the power source leads can be reduced and hence, thesemiconductor device can be miniaturized.

[0118]FIG. 34(a) and FIG. 34(b) are views showing the inner structure ofa semiconductor device according to a modification 4 of this embodiment1 of the present invention, wherein FIG. 34(a) is a schematic plan viewand FIG. 34(b) is a schematic cross-sectional view. As shown in thesedrawings, the bonding wire 8 c may be continuously formed in a closedring shape.

[0119] (Embodiment 2)

[0120] In the abovementioned embodiment 1, the explanation is made withrespect to the example in which the number of the power source leads isreduced using the bonding wires. In this embodiment 2, the explanationis made with respect to an example in which the number of the powersource leads is reduced using relay bonding pads and bonding wires.

[0121]FIG. 15(a) and FIG. 15(b) are views showing the inner structure ofa semiconductor device according to an embodiment 2 of the presentinvention, wherein FIG. 15(a) is a schematic plan view and FIG. 15(b) isa schematic cross-sectional view.

[0122]FIG. 16(a) and FIG. 16(b) are views showing the inner structure ofthe semiconductor device according to the embodiment 2 of the presentinvention, wherein FIG. 16(a) is a schematic cross-sectional view alonga signal lead and FIG. 16(b) is a schematic cross-sectional view along apower source lead.

[0123]FIG. 17 is a schematic plan view showing a portion of FIG. 15(a)in an enlarged manner.

[0124]FIG. 18 is a schematic plan view showing a portion of FIG. 17 inan enlarged manner;

[0125]FIG. 19 is a schematic plan view showing a portion of FIG. 17 inan enlarged manner.

[0126]FIG. 20 is a planar layout view of a semiconductor chip shown inFIG. 15(a).

[0127]FIG. 21 is a planar layout view showing a portion of FIG. 20 in anenlarged manner.

[0128]FIG. 22 is a schematic cross-sectional view showing the innerstructure of the semiconductor chip in FIG. 20.

[0129] As shown in FIG. 21, a plurality of buffer cells 4 include aplurality of power source cells 4 b 2 and a plurality of bonding pads 3include a plurality of power source bonding pads 3 b 2. The plurality ofpower source cells 4 b 2 are arranged corresponding to the plurality ofpower source bonding pads 3 b 2.

[0130] Although not shown in the drawing, on an internal circuit formingportion 10, a power source line which supplies an operational potential(for example, 0V=Vss) to a plurality of input/output cells 4 a, forexample, is arranged. This power source line extends in a ring-likeshape such that the power source line surrounds the internal circuitforming portion 10 in plane.

[0131] The power source bonding pads 3 b 2 are electrically connectedwith the corresponding power source cells 4 b 2. Further, the pluralityof power source cells 4 b 2 are electrically connected with theabovementioned power source line. The power source line is electricallyconnected with the plurality of input/output cells 4 a. The power sourcecells 4 b 2 are cells served for supplying an operational potentialnecessary for a circuit operation of the input/output cells 4 a.

[0132] The plurality of power source bonding pads 3 b 2 are arrangedsuch that the power source bonding pads 3 b 2 sandwich a plurality ofsignal bonding pads 3 a in plane for enabling the plurality ofinput/output cells 4 a to perform a stable operation.

[0133] As shown in FIG. 20 and FIG. 21, on a main surface 2 x of thesemiconductor chip 2, a relay pad 3 c is arranged. The relay pad 3 c isarranged in a channel forming region 13 defined between circuit blocks12 and, at the same time, on a region where transistor dies are notformed, that is, on an element separation insulation film (fieldinsulation film) 21. In this embodiment 2, the relay pad 3 c is arrangedin the vicinity of a center point where two diagonal lines of thesemiconductor chip 2 cross each other, for example.

[0134] As shown in FIG. 16 to FIG. 19, a plurality of leads 5 include aplurality of signal leads 5 a and, further, include one power sourcelead 5 b 2 to which an operational potential Vss of 0 [V], for example,is applied. A plurality of bonding wires 8 include a plurality ofbonding wires 8 a which respectively electrically connect the pluralityof signal bonding pads 3 a of the semiconductor chip 2 and the pluralityof signal leads 5 a respectively. The plurality of bonding wires 8further include the bonding wire 8 b 2 which electrically connects thearbitrary power source bonding pad 3 b 2 out of the plurality of powersource bonding pads 3 b 2 of the semiconductor chip 2 with the powersource lead 5 b 2. The plurality of bonding wires 8 further include aplurality of bonding wires 8 d which electrically connect the powersource bonding pads 3 b 2 having the same function of the semiconductorchip 2 with the relay pad (relay bonding pad) 3 c.

[0135] As shown in FIG. 18 and FIG. 19, arbitrary power source bondingpads 3 b 2 out of the plurality of power source bonding pads 3 b 2 areelectrically connected with the power source leads 5 b 2 via the bondingwires 8 b 2, while the plurality of power source bonding pads 3 b 2which include these arbitrary power source bonding pads 3 b 2 areelectrically connected with the relay pad 3 c via the bonding wires 8 d.Due to such a constitution, except for the arbitrary power sourcebonding pads 3 b 2, the number of power source leads 5 b 2 can bereduced by an amount corresponding to the number of the power sourcebonding pads 3 b 2 which are electrically connected with the relay pad 3c via the bonding wires 8 d and hence, the miniaturization of thesemiconductor device can be realized. According to this embodiment 2,for example, while 24 power source bonding pads 3 b 2 are provided, onepower source lead 5 b 2 is connected with one of the power sourcebonding pads 3 b 2 via the bonding wires 8 b 2 and hence, 23 powersource leads 5 b 2 can be reduced.

[0136] The bonding wires 8 a are, as shown in FIG. 16(a), connected by anail head bonding (ball bonding) method which performs the primaryconnection at the signal bonding pads 3 a of the semiconductor chip 2and performs the secondary connection at the signal leads 5 a.

[0137] The bonding wires 8 b 2 are, as shown in FIG. 18, connected by anail head bonding (ball bonding) method which performs the primaryconnection at the power source leads 5 b 2 and performs the secondaryconnection at the power source bonding pads 3 b 2 of the semiconductorchip 2.

[0138] The bonding wires 8 d are, as shown in FIG. 16(b), connected by anail head bonding method which performs the primary connection at thepower source bonding pads 3 b 2 with the secondary connection at therelay pad 3 c. In this manner, by performing the wire connection betweenthe power source bonding pads 3 b 2 and the relay pads 3 c by the nailhead bonding method which performs the primary connection at the powersource bonding pads 3 b 2 and the secondary connection at the relay pad3 c, a height of the bonding wires 8 d on the relay pad 3 c can belowered and hence, a distance between a capillary at the time ofconnecting the bonding wires 8 d to the relay pad 3 c and the bondingwires 3 d which are already connected can be broadened. As a result,compared to a case in which the relay pad 3 c and the power sourcebonding pads 3 b 2 are connected using wires by the nail head bondingmethod which performs the primary connection at the relay pad 3 c andthe secondary connection at the power source bonding pads 3 b 2, an areaof the relay pad 3 c can be reduced. Accordingly, it is possible toeasily arrange the relay pad 3 c without increasing the size of thesemiconductor chip 2 and without receiving the restriction on designing.Further, the plurality of bonding wires 8 d can be connected to therelay pad 3 c in a concentrated manner with a small area.

[0139] The relay pad 3 c is arranged in a wiring channel region 13 inwhich a transistor die which constitutes a circuit is not formed. Due tosuch a constitution, it is possible to suppress the occurrence of adefect attributed to impacts which the semiconductor device receives atthe time of connecting the bonding wires 8 d to the relay pad 3 c.

[0140] (Embodiment 3)

[0141] This embodiment 3 is directed to an example in which the numberof leads is reduced by the combination of the abovementioned embodiments1 and 2.

[0142]FIG. 23(a) and FIG. 23(b) are views showing the inner structure ofa semiconductor device according to an embodiment 3 of the presentinvention, wherein FIG. 23(a) is a schematic plan view and FIG. 23(b) isa schematic cross-sectional view;

[0143] As shown in FIG. 23, the wire connection between bonding pads towhich an operational potential (power source potential) Vcc is appliedis established using the abovementioned embodiment 1 and the wireconnection between bonding pads to which an operational potential (powersource potential) Vss is applied is established using the abovementionedembodiment 2. In this manner, due to the combination of theabovementioned embodiments 1 and 2, the number of the power source leadsof two systems can be reduced and hence, it is possible to realize thefurther miniaturization of the semiconductor device.

[0144] (Embodiment 4)

[0145] This embodiment 4 is directed to an example in which the numberof leads is reduced by combining the above-mentioned embodiment 1 and abus bar lead.

[0146]FIG. 24(a) and FIG. 24(b) are views showing the inner structure ofa semiconductor device according to an embodiment 4 of the presentinvention, wherein FIG. 24(a) is a schematic plan view and FIG. 24(b) isa schematic cross-sectional view.

[0147] The semiconductor device of this embodiment 4 is configured toinclude a bus bar lead 17. The bus bar lead 17 is arranged between sidesof a semiconductor chip 2 and one-end portions of a plurality of leads 5and, at the same time, along the sides of the semiconductor chip 2. Inthis embodiment 4, the bus bar lead 17 is arranged along four sides ofthe semiconductor chip 2 and is integrally connected with foursuspending leads 7. Further, the bus bar lead 17 is arranged to beconnected with four suspending leads 7 in a region outside thesemiconductor chip 2.

[0148] On the semiconductor chip 2, a plurality of power source pads 3 bare electrically connected with power source leads 5 b to which anoperational potential Vcc (for example, 3.3V) is applied by adopting thewire connection substantially equal to the wire connection adopted bythe abovementioned embodiment 1.

[0149] The bus bar lead 17 is electrically connected with power sourceleads 5 b 2 to which an operational potential Vss (for example, 0V)which is lower than the operational potential Vcc is supplied usingbonding wires 8 b 2.

[0150] A plurality of power source bonding pads 3 b 2 to which theoperational potential Vss is supplied are electrically connected withthe bus bar lead 17 by a plurality of bonding wires 8 e.

[0151] In this manner, by electrically connecting the plurality of powersource bonding pads 3 b with power source leads 5 b 2 to which theoperational potential Vcc is supplied using the wire connectionsubstantially equal to the wire connection adopted by the abovementionedembodiment 1, by electrically connecting the bus bar lead 17 with thepower source leads 5 b 2 to which the operational potential Vss which islower than the operational potential Vcc is supplied using bonding wires8 b 2, and by electrically connecting the plurality of power sourcebonding pads 3 b 2 with the bus bar lead 17 using the plurality ofbonding wires 8 e, it is possible to reduce the number of the powersource leads of two systems in the same manner as thepreviously-mentioned embodiment 3 and hence, it is possible to realizethe further miniaturization of the semiconductor device.

[0152] Here, as shown in FIG. 35(a) and FIG. 35(b), another bus bar lead50 may be further formed besides the bus bar lead 17. In this case,another bus bar lead 50 is integrally formed with the selected leads 5and an operational potential Vss is supplied to another bus bar lead 50from the outside.

[0153] (Embodiment 5)

[0154] In the embodiment 5, the explanation is made with respect to anexample in which the invention is applied to a QFN (Quad FlatpackNon-leaded Package) type semiconductor device.

[0155]FIG. 25(a) and FIG. 25(b) are views showing the inner structure ofthe semiconductor device according to the embodiment 5 of the presentinvention, wherein FIG. 25(a) is a schematic plan view and FIG. 25(b) isa schematic cross-sectional view.

[0156] The semiconductor device of the embodiment 5 is configured suchthat a plurality of leads 5 are exposed from a back surface of thesealing body 9.

[0157] A plurality of power source bonding pads 3 b of the semiconductorchip 2 adopt the wire connection substantially equal to the wireconnection of the abovementioned embodiment 1, wherein the power sourcebonding pads 3 b are electrically connected with power source leads 5 bto which a Vcc operational potential (for example, 3.3V) is supplied.

[0158] A plurality of power source bonding pads 3 b 2 of thesemiconductor chip 2 adopt the wire connection substantially equal tothe wire connection of the abovementioned embodiment 2, wherein thepower source bonding pads 3 b 2 are electrically connected with powersource leads 5 b 2 to which an operational potential Vss (for example,0V) is supplied.

[0159] In this manner, the plurality of power source bonding pads 3 bare electrically connected with the power source leads 5 b to which theoperational potential Vcc is supplied using the wire connectionsubstantially equal to the wire connection of the abovementionedembodiment 1, and the plurality of power source bonding pads 3 b 2 areelectrically connected with the power source leads 5 b 2 to which theoperational potential Vss which is lower than the operational potentialVcc is supplied using the wire connection substantially equal to thewire connection of the abovementioned embodiment 2 and hence, also withrespect to the QFN type semiconductor device, the number of the powersource leads can be reduced and the semiconductor device can beminiaturized.

[0160] Here, the explanation is made with respect the example which usesthe lead frame which is half-etched such that the tabs have a thicknesswhich is 50% of a thickness of the frame. However, even with respect tothe QFN type semiconductor device which uses tab elevating structure orthe tab exposing structure, it is possible to reduce the number of thepower source leads in the same manner whereby the miniaturization of thesemiconductor device be realized.

[0161] (Embodiment 6)

[0162] In the embodiment 6, the explanation is made with respect to anexample in which the present invention is applied to a BGA (Ball GridArray) type semiconductor device.

[0163]FIG. 26(a) and FIG. 26(b) are views showing the inner structure ofthe semiconductor device according to the embodiment 6 of the presentinvention, wherein FIG. 26(a) is a schematic plan view and FIG. 26(b) isa schematic cross-sectional view.

[0164] The semiconductor device of the embodiment 6 is configured, asshown in FIG. 26, such that the semiconductor device mainly includes asemiconductor chip 2, a plurality of bonding wires 8, a printed wiringcircuit board 30, a plurality of projection-like electrodes (bumpelectrodes) 32 which are used as external connection terminals and thelike. The semiconductor chip 2 is adhered to and is fixed to the mainsurface of the printed wiring circuit board 30 by interposing anadhesive material therebetween. A plurality of projection-likeelectrodes 32 are arranged in a matrix array on a back surface oppositeto the main surface of the printed wiring circuit board 30.

[0165] A plurality of connecting portions 31 are arranged in a peripheryof the semiconductor chip 2. The plurality of connecting portion 31 areconstituted of portions of lines of the printed wiring circuit board 30,and the plurality of connecting portion 31 are arranged corresponding toa plurality of bonding pads 3 of the semiconductor chip 2.

[0166] The plurality of connecting portions 31 are respectivelyelectrically connected with projection-like electrodes 32 via lines ofthe printed wiring circuit board 30. The plurality of connectingportions 31 include a plurality of a signal connecting portions, a powersource connecting portion 31 b, and a power source connecting portion 31b 2.

[0167] A plurality of a signal bonding pads 3 a of the semiconductorchip 2 are electrically connected with a plurality of the signalconnecting portions of the printed wiring circuit board 30 via thebonding wires 8.

[0168] A plurality of power source bonding pads 3 b of the semiconductorchip 2 adopt the wire connection substantially equal to the wireconnection of the abovementioned embodiment 1, wherein the power sourcebonding pads 3 b are electrically connected with the power sourceconnecting portion 31 b to which an operational potential Vcc (forexample, 3.3V) is supplied.

[0169] A plurality of power source bonding pads 3 b 2 of thesemiconductor chip 2 adopt the wire connection substantially equal tothe wire connection of the abovementioned embodiment 2, wherein thepower source bonding pads 3 b 2 are electrically connected with thepower source connecting portion 31 b 2 to which an operational potentialVss (for example, 0V) is supplied.

[0170] The semiconductor chip 2, a plurality of bonding wires 8 and thelike are sealed by a sealing body 9 which selectively covers a mainsurface of the printed wiring circuit board 30. The sealing body 9 isformed using a single surface molding technique.

[0171] In this manner, a plurality of power source bonding pads 3 b areelectrically connected with the power source connecting portion 31 b towhich the operational potential Vcc is supplied using the wireconnection substantially equal to the wire connection of theabovementioned embodiment 1, and the plurality of power source bondingpads 3 b 2 are electrically connected with the power source connectingportion 31 b 2 to which the operational potential Vss which is lowerthan the operational potential Vcc is supplied using the wire connectionsubstantially equal to the wire connection of the abovementionedembodiment 2 and hence, the number of the power source connectingportions (31 b, 31 b 2) can be reduced whereby the miniaturization ofthe printed wiring circuit board 30 can be realized and, at the sametime, the miniaturization of the semiconductor device can be realized.

[0172] Further, even when the present invention is applied to thesemiconductor device without aiming at the reduction of the size of thesemiconductor device, it is possible to widen a pitch of solder bowls 32which constitute external terminals. Accordingly, narrowing of the pitchof the printed wiring circuit board (mounting board) for mounting thepackage can be alleviated and hence, mounting of the package on theprinted wiring circuit board is facilitated. Further, a width of wiringformed on the printed wiring circuit board 30 can be increased andhence, the reliability of the package can be enhanced.

[0173] Further, as shown in FIG. 36(a) and FIG. 36(b), a plurality ofconnecting portions 31 may be arranged in a staggered pattern. In thiscase, an interval of a plurality of neighboring connecting portions 31can be reduced compared to the embodiment shown in FIG. 26 and hence, aplanner size of the wiring board 30 can be reduced whereby theminiaturization of the package can be realized correspondingly. Further,the power source connecting portion 31 b 2 can be arranged close to(inside) the semiconductor chip and a length of the bonding wires to beconnected is arranged to become short.

[0174] Further, as shown in FIG. 37(a) and FIG. 37(b), bus bar lines 51(operational potential Vss, for example 0V) and bus bar lines 52(operational potential Vcc, for example 3.3V) may be formed around thesemiconductor chip 2, and for the same purpose that the example shown inFIG. 35(a) and FIG. 35(b) is provided to achieve, the bus bar lines 51and 52 may be connected with a plurality of corresponding power sourcebonding pads and a plurality of corresponding power source connectingportions using bonding wires.

[0175] Further, as shown in FIG. 38(a) and FIG. 38(b), the semiconductordevice may adopt the structure in which the printed wiring circuit board30 and the sealing body 9 are formed to have the same size in a planview and a plurality of projection-like electrodes (bump electrodes) 32are omitted. Such a structure is obtained by forming the sealing bodyusing a MAP (Multi Arrayed Package) technique (also referred to as acollective molding technique) and, thereafter, by dicing a multi-wiringsubstrate. Further, the omission of the plurality of projection-likeelectrodes (bump electrodes) 32 may be compensated by using a backgroundmetal layer 32 a of a bump electrode forming portion (for example, theAu plating structure on a Cu layer). Such an electrode structure isgenerally referred to as the LGA (Land Grid Array) structure.

[0176] (Embodiment 7)

[0177] In this embodiment 7, the explanation is made with respect to asemiconductor device having a semiconductor chip provided with testingbonding pads.

[0178]FIG. 27 is a schematic plan view showing the inner structure of asemiconductor device according to an embodiment 7 of the presentinvention.

[0179]FIG. 28 is a schematic plan view of a portion of FIG. 27 in anenlarged manner.

[0180]FIG. 29 is a planar layout view of a semiconductor chip shown inFIG. 27.

[0181]FIG. 30 is a plan view of a semiconductor wafer used in themanufacture of the semiconductor device of the embodiment 7.

[0182]FIG. 31 is a view for explaining a characteristics inspection stepin the manufacture of the semiconductor device in the embodiment 7.

[0183] As shown in FIG. 29, an internal circuit of a semiconductor chip2 includes a testing circuit 12 a for electrically testing functions ofthe circuit blocks 12. Further, a plurality of bonding pads 3 formed onthe semiconductor chip 2 include a testing bonding pad 3 d which iselectrically connected with the testing circuit 12 a via internal wiringof the semiconductor chip 2.

[0184] As shown in FIG. 27 and FIG. 28, the plurality of bonding pads 3which include the testing bonding pad 3 d are electrically connectedwith the power source leads 5 b 2 to which an operational potential Vss(for example, 0V) is supplied using the wire connection substantiallysimilar to the wire connection used in the previously-mentionedembodiment 2. That is, the operational potential Vss is supplied fromthe power source lead 5 b 2 to the testing bonding pad 3 d through thebonding wire 8 b 2, the power source bonding pad 3 b 2, the bonding wire8 d, the relay pad 3 c and the bonding wire 8 d.

[0185] The semiconductor chip 2 is formed by dividing a semiconductorwafer 40 shown in FIG. 30 into individual parts in a dicing step duringa manufacturing process of the semiconductor device. The semiconductorwafer 40 is configured to have a plurality of chip forming regions 42defined by scribe lines 41. By dicing the scribe lines 41 thus dividingthe semiconductor wafer 40 into a plurality of individual chip formingregions 42, the semiconductor chips 2 each of which is constituted ofthe chip forming region 42 are formed.

[0186] A test for electrically testing the functions of the circuitblock 12 of the semiconductor chip 2 is performed when the semiconductorchip 2 is in a state of the semiconductor wafer 40. As shown in FIG. 31,the test is performed in such a manner that a probe needle 45 of a probecard which is electrically connected with a testing device is broughtinto contact with the testing pad 3 d. The testing circuit 12 a shown inFIG. 29 is used in an inspection step which is conducted before dividingthe semiconductor wafer 40 into individual parts and is not used afterassembling the semiconductor chip 2 into the semiconductor devicespecifically. That is, the testing circuit 12 a is operated when thesemiconductor chip 2 is in a state of the semiconductor wafer state 40and is inoperable when the semiconductor chip 2 is in a state of thesemiconductor chip 2.

[0187] In an actual operation after assembling the semiconductor chip 2into the semiconductor device, the testing circuit 12 a is inoperable.However, when the testing circuit 12 a assumes a floating state in termsof potential, this may become a cause of a drawback that the internalcircuit performs an erroneous operation. Accordingly, the potential ofthe testing circuit 12 a is usually fixed.

[0188] The plurality of bonding pads 3 which include the testing bondingpad 3 d are electrically connected with the power source leads 5 b 2 towhich the operational potential Vss (for example, 0V) is supplied byusing the wire connection substantially similar to the wire connectionused in the previously-mentioned embodiment 2. Accordingly, even whenthe power source lead 5 b which is provided for the testing bonding padconventionally is omitted, the potential of the testing circuit can befixed in the actual use and hence, even when the semiconductor device isminiaturized by reducing the number of power source leads 5 b, it ispossible to provide the highly reliable semiconductor device whichexhibits the stable operation.

[0189] (Embodiment 8)

[0190]FIG. 32 is a schematic plan view showing the inner structure of asemiconductor device according to an embodiment 8 of the presentinvention.

[0191] As shown in FIG. 32, an internal circuit of the semiconductorchip 2 includes a clock circuit 17. Further, a plurality of bonding padsformed on the semiconductor chip 2 include a clock signal pad (clocksignal bonding pad) 3 e which is electrically connected with an inputterminal of the clock circuit 17 via inner wiring of the semiconductorchip 2. Further, a bonding pad 18 which constitutes an output terminalof the clock circuit 17 is arranged on a main surface of thesemiconductor chip 2.

[0192] The clock signal pad 3 e is electrically connected with thesignal lead 5 c to which a reference signal is supplied from the outsidevia a bonding wire 8 f. Respective blocks 12 are provided with clockinput terminals 19 and these clock input terminals 19 are electricallyconnected with the bonding pad 18 (output terminal of clock circuit 17)via the bonding wire 8 e. That is, the reference clock signal suppliedfrom the outside is inputted to the input terminal of the clock circuit17 via the signal lead 5 c, the bonding wire 8 f and the clock signalpad 3 e, while a clock signal outputted from an output terminal of theclock circuit 17 is inputted to the plurality of respective circuitblocks 12 via the bonding wires 18 e.

[0193] In this manner, by respectively connecting the bonding pad 18which constitutes the output terminal of the clock circuit 17 with theclock input terminals 19 of the plurality of circuit blocks using theplurality of bonding wires 8 e, compared to a case in which a supplypath of a clock signal is formed by wiring on a thin film chip formed bya wafer process, the connection resistance can be lowered and hence, amargin for designing of timing can be increased. Further, the freedom oflayout designing can be enhanced with respect to the supply path of theclock signal and hence, a chip area can be reduced.

[0194] (Embodiment 9)

[0195]FIG. 42 is a schematic plan view showing the inner structure of asemiconductor device according to an embodiment 9 of the presentinvention. Although the semiconductor device basically has thesubstantially same constitution as the constitution of the semiconductordevice explained in conjunction with FIG. 32, the constitutional featureof this embodiment lies in that switching circuits SMC1, SMC2 which canchange capacitances of RAM1 to RAM4 depending on the specification ofcustomers are mounted on a main surface of the chip. In this embodiment,the explanation is made with respect to a case that the capacitances ofRAM1 to RAM4 are changed in a stage of wire bonding.

[0196] The switching circuits SMC1, SMC2 are circuit blocks which arereferred to as soft modules such as system control circuits, bus controlcircuits and the like. For example, as shown in FIG. 43, the switchingcircuit SMC1 supplies an output signal to a changeover bonding pad SPD2in response to an input signal In1 or supplies an output signal to achangeover bonding pad SPD3 in response to an input signal In2.

[0197] On the other hand, in response to inputting of the output signalsupplied to one of the changeover bonding pad SPD2 and the changeoverbonding pad SPD3 into a changeover bonding pad SPD1 via the bonding wireSWB, the switching circuit SMC2 supplies a given output signal Out1(CS1, CS2) to the RAM1 to the RAM4.

[0198] This example shows a case in which by connecting the changeoverbonding pads SPD3 and SPD1 to each other using a bonding wire SWB, thecircuit blocks 12 of all RAM1 to RAM4 are selected in response to theabovementioned output signal Out1 (CS1, CS2) and, the capacitances of 4Kbites, for example, can be obtained. Further, when the changeoverbonding pads SPD3 and SPD1 are connected to each other using a bondingwire SWB, only the RAM1 and the RAM2 are selected and hence, thecapacitances of 2K bite, for example, can be obtained.

[0199] As the abovementioned bonding wire SWB, the bonding wire 8explained in conjunction with the abovementioned embodiments 1 to 7 isapplicable. Further, the changeover bonding pads SPD1 to SPD3 can beformed by steps substantially equal to the steps of forming the bondingpads 3 c explained in conjunction with FIG. 22. In this manner, thespecification of the clients can be changed over at the wire bondingstage and hence, for example, compared to a technique which determinesthe specification of clients in a step of forming multi-layered wiringof an IC chip (for example, a master slicing step of aluminum wiring),it is possible to enhance the TAT (Turn Around Time) of the productdevelopment and, at the same time, no particular steps are required forperforming this embodiment.

[0200] Further, although the explanation is made only with respect tothe changeover of the RAM capacitances in this embodiment, thisembodiment is applicable to the changeover of other chip functions (forexample, ROM capacitances, presence or non-presence of ROMs, gain of I/Obuffer).

[0201] Although the invention made by inventors of the present inventionhas been specifically explained in conjunction with the abovementionedembodiments, it is needless to say that the present invention is notlimited to the above-mentioned embodiments and various modifications canbe made without departing from the gist of the present invention.

[0202] For example, although the supply of power source to the internalcircuit 12 is performed by the power source line 15 in FIG. 14, portionsof the power source line 15 may be replaced with the bonding wires 8 eand the operational potential may be supplied to the respective internalcircuits (modules) via the abovementioned replacing bonding wires. Inthis case, power source inputting terminals dedicated to respectiveinternal circuits may be formed using the structure substantially equalto the structure of the pads 3 c shown in FIG. 22, and ends on one sideof the replacing bonding wire 8 e may be connected to the dedicatedpower source inputting terminals. Due to such a constitution, theportions of the power source line 15 which are formed inside thesemiconductor chip become unnecessary thus contributing to shrinking ofthe semiconductor chip. Further, the wiring resistance is lowered andhence, the potential can be supplied in a stable manner.

[0203] Further, when the abovementioned dedicated power source inputtingterminals and the like are formed on the semiconductor chip and theseare connected to each other by the bonding wires 8 e, as shown in FIG.39(a) and FIG. 39(b), by arranging the abovementioned dedicated powersource inputting terminals in the inflow direction of the resin injectedfrom a resin injection gate G at the time of forming the sealing body 9,the flowing-away of the bonding wires 8 e which connect these terminalsto each other can be made difficult. Accordingly, the connection betweenthe wires and the disconnection of the wires can be prevented whereby itis possible to provide the electrically highly reliable package.

[0204] Further, as shown in FIG. 40(a) and FIG. 40(b), the bonding wires8 c which connect between the power source bonding pads may be partiallyapplied in plural numbers at four corners of the semiconductor chip.

[0205] Further, as shown in FIG. 41(a) and FIG. 41(b), a secondsemiconductor chip 40 may be further stacked on a main surface of thesemiconductor chip 2, and the constitution of each embodiment may beapplied to the stacked second semiconductor chip 40.

[0206] In this case, although not shown in the drawing, signal padsformed on the second semiconductor chip 40 are connected to the signalpads 3 a formed on the first semiconductor chip 2 disposed below thesecond semiconductor chip 40 by way of bonding wires or are directlyconnected to the signal leads 5 a using bonding wires.

[0207] Further, although not shown in the drawing, the present inventionmay be applicable to a MCP (Multi Chip Package) which mounts a pluralityof semiconductor chips on a printed wiring circuit board in plane andhouses the semiconductor chips in one package.

[0208] To briefly recapitulate the advantageous effects obtained byrepresentative inventions among the present inventions disclosed in thisspecification, they are as follows.

[0209] According to the present inventions, it is possible tominiaturize the semiconductor device.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor chip having a main surface; an internal circuit which isformed on the main surface of the semiconductor chip; an interfacecircuit which is formed on the main surface of the semiconductor chipand includes a plurality of I/O cells which are arranged to surround theinternal circuit in plane; a plurality of bonding pads which are formedon the main surface of the semiconductor chip, are arranged between theinterface circuit and sides of the semiconductor chip and include firstpower source bonding pads, second power source bonding pads and aplurality of signal bonding pads; power source wiring which is formed onthe main surface of the semiconductor chip, is connected to the firstand second power source bonding pads in common, and supplies anoperational potential to the plurality of I/O cells; a plurality ofleads which are arranged around the semiconductor chip and include firstpower source leads and a plurality of signal leads; a plurality ofbonding wires which include first bonding wires for connecting the firstpower source bonding pads with the first power source leads, secondbonding wires for connecting the first power source bonding pads withsecond power source bonding pads and a plurality of third bonding wiresfor connecting a plurality of signal bonding pads with the plurality ofsignal leads; and a sealing body which seals the semiconductor chip, theplurality of bonding wires and some of the plurality of leads.
 2. Thesemiconductor device according to claim 1, wherein respective electricresistances of the plurality of bonding wires are lower than an electricresistance of the power source wiring.
 3. The semiconductor deviceaccording to claim 1, wherein the power source wiring extends along adirection of an arrangement of the plurality of I/O cells.
 4. Thesemiconductor device according to claim 1, wherein the first and secondpower source bonding pads are arranged to sandwich the plurality ofsignal bonding pads in plane.
 5. The semiconductor device according toclaim 1, wherein the interface circuit further includes a plurality ofpower source cells, and wherein the first and second power sourcebonding pads are connected to selected power source cells among theplurality of power source cells.
 6. The semiconductor device accordingto claim 1, wherein the second power source bonding pads are notconnected to the plurality of leads.
 7. The semiconductor deviceaccording to claim 1, wherein the plurality of leads extend toward theoutside and the inside of the sealing body and project from a sidesurface of the sealing body.
 8. The semiconductor device according toclaim 1, wherein the sealing body includes a main surface which ispositioned at a side at which the main surface of the semiconductor chipis positioned and a back surface which is positioned at a side oppositeto the main surface, and wherein the plurality of leads are exposed froma back surface of the sealing body.
 9. A semiconductor devicecomprising: a semiconductor chip; a plurality of I/O cells which areformed along sides of the semiconductor chip; a plurality of bondingpads which are formed between the plurality of I/O cells and sides ofthe semiconductor chip; a plurality of leads which are arranged aroundthe semiconductor chip; first bonding wires which electrically connectthe plurality of leads with the plurality of bonding pads; and secondbonding wires which electrically connect arbitrary bonding pads to eachother among the plurality of bonding pads.
 10. A semiconductor devicecomprising: a semiconductor chip having a main surface; an internalcircuit which is formed on the main surface of the semiconductor chip;an interface circuit which is formed on the main surface of thesemiconductor chip and includes a plurality of I/O cells which arearranged to surround the internal circuit in plane; a plurality ofbonding pads which are formed on the main surface of the semiconductorchip, are arranged between the interface circuit and sides of thesemiconductor chip and include first power source bonding pads, secondpower source bonding pads and a plurality of signal bonding pads; powersource wiring which is formed on the main surface of the semiconductorchip, is connected to the first and second power source bonding pads incommon, and supplies an operational potential to the plurality of I/Ocells; a printed wiring circuit board which mounts the semiconductorchip on a first surface thereof, and has a plurality of connectingportions including first power source connecting portions which arearranged around the mounted semiconductor chip and a plurality of signalconnecting portions; a plurality of bonding wires which include firstbonding wires for connecting the first power source bonding pads withthe first power source connecting portions, second bonding wires forconnecting the first power source bonding pads with second power sourcebonding pads and third bonding wires for connecting the plurality ofsignal bonding pads with the plurality of signal leads; a plurality ofprojection-like electrodes which are arranged on a second surface of theprinted wiring circuit board which faces the first surface of theprinted wiring circuit board in an opposed manner and are electricallyconnected with the plurality of connecting portions of the printedwiring circuit board, and a sealing body which seals the semiconductorchip, the plurality of bonding wires and the first surface of theprinted wiring circuit board.
 11. The semiconductor device according toclaim 10, wherein respective electric resistances of the plurality ofbonding wires are lower than an electric resistance of the power sourcewiring.
 12. A semiconductor device comprising: a semiconductor chiphaving a main surface; an internal circuit which is formed on the mainsurface of the semiconductor chip; an interface circuit which is formedon the main surface of the semiconductor chip and includes a pluralityof I/O cells which are arranged to surround the internal circuit inplane; a plurality of bonding pads which are formed on the main surfaceof the semiconductor chip, are arranged between the interface circuitand sides of the semiconductor chip and include first power sourcebonding pads, second power source bonding pads, a plurality of thirdpower source bonding pads and a plurality of signal bonding pads; powersource wiring which is formed on the main surface of the semiconductorchip, is connected to the first and second power source bonding pads incommon, and supplies an operational potential to the plurality of I/Ocells; a plurality of leads which are arranged around the semiconductorchip and have a plurality of first leads including first power sourceleads and a plurality of signal leads and second leads which arearranged between sides of the semiconductor chip and one end portions ofthe plurality of first leads and are arranged along the sides of thesemiconductor chip; a plurality of bonding wires which include firstbonding wires for connecting the first power source bonding pads withthe first power source leads, second bonding wires for connecting thefirst power source bonding pads with second power source bonding pads,third bonding wires for connecting a plurality of signal bonding padswith the plurality of signal leads, and a plurality of fourth bondingwires for connecting the plurality of third power source bonding padswith the second leads; and a sealing body which seals the semiconductorchip, the plurality of bonding wires and some of the plurality of leads,wherein the first power source leads are leads to which a firstoperational potential is supplied, and the second power source leads areleads to which a second operational potential which is lower than thefirst operational potential is supplied.
 13. The semiconductor deviceaccording to claim 12, wherein the semiconductor chip has a quadrangularshape, and wherein the second leads are arranged along four sides of thesemiconductor chip.
 14. The semiconductor device according to claim 13,wherein the semiconductor device further includes a chip mountingportion and four suspending leads which are integrally formed with thechip mounting portion, and wherein the second leads are arranged toallow the four suspending leads to be connected in a region outside thesemiconductor chip.
 15. A semiconductor device comprising: asemiconductor chip having a main surface; an internal circuit which isformed on the main surface of the semiconductor chip and includes aplurality of logic circuit blocks and a clock circuit; an interfacecircuit including a plurality of I/O cells which is formed on the mainsurface of the semiconductor chip and is arranged to surround theinternal circuit in plane; a plurality of bonding pads which are formedon the main surface of the semiconductor chip and are arranged alongsides of the semiconductor chip; a plurality of leads which are arrangedaround a periphery of the semiconductor chip; a plurality of firstbonding wires which connect the plurality of bonding pads with theplurality of leads; a plurality of second bonding wires which connectclock output terminals of the clock circuit and clock input terminals ofthe plurality of logic circuit blocks to each other; and a sealing bodywhich seals the semiconductor chip, the plurality of first and secondbonding wires and some of the plurality of leads, wherein clock signalswhich are outputted from the clock circuit are inputted to the pluralityof respective logic circuit blocks via the second bonding wires.
 16. Thesemiconductor device according to claim 15, wherein the plurality ofbonding pads include clock signal pads to which a reference clock signalis inputted, and wherein the reference clock signal is inputted to theclock signal via a given line which is formed in the semiconductor chip.17. A semiconductor device comprising: a semiconductor chip having amain surface; an internal circuit which is formed on the main surface ofthe semiconductor chip and includes a logic circuit block and a testingcircuit for electrically testing functions of the logic circuit block;an interface circuit which is formed on the main surface of thesemiconductor chip and includes a plurality of I/O cells which arearranged to surround the internal circuit in plane; a plurality ofbonding pads which are formed on the main surface of the semiconductorchip, are arranged between the interface circuit and sides of thesemiconductor chip and include power source bonding pads, testing powersource bonding pads and a plurality of signal bonding pads; a pluralityof leads which are arranged around the semiconductor chip and includepower source leads and a plurality of signal leads; a plurality ofbonding wires which include first bonding wires for connecting the powersource bonding pads with the power source leads, second bonding wiresfor connecting the power source bonding pads with the testing bondingpads and third bonding wires for connecting the plurality of signalbonding pads with the plurality of signal leads; and a sealing bodywhich seals the semiconductor chip, the plurality of bonding wires andsome of the plurality of leads.
 18. The semiconductor device accordingto claim 17, wherein the semiconductor chips are formed by dicing asemiconductor wafer which includes a plurality of semiconductor chipforming regions defined by scribe lines along the scribe lines, andwherein a test for electrically testing the functions of the logiccircuit blocks is performed when the semiconductor chip is in asemiconductor wafer state.
 19. The semiconductor device according toclaim 18, wherein the testing circuit is operated when the semiconductorchip is in the semiconductor wafer state and is not operated when thesemiconductor chip is in a semiconductor chip state.
 20. A semiconductordevice comprising: a semiconductor chip which has first and secondbonding pads on a main surface thereof, connecting portions which arearranged around the semiconductor chip; first bonding wires whichelectrically connect first bonding pads of the semiconductor chip withthe connecting portions; second bonding wires which electrically connectthe first bonding pads with the second bonding pads of the semiconductorchip; and a sealing body which seals the semiconductor chip, theconnecting portions, the first and the second bonding wires.
 21. Thesemiconductor device according to claim 20, wherein the first and thesecond bonding pads are arranged along one side of the semiconductorchip.
 22. The semiconductor device according to claim 20, wherein thefirst bonding pads are arranged at a first side of the semiconductorchip, and wherein the second bonding pads are arranged at a second sideof the semiconductor chip opposite to the first side of thesemiconductor chip.
 23. A semiconductor device according to claim 20,wherein the first bonding pads are arranged at the first side of thesemiconductor chip, and wherein the second bonding pads are arranged ata second side of the semiconductor chip adjacent to the first side ofthe semiconductor chip.
 24. The semiconductor device according to claim20, wherein the first bonding pads include first and second regions,wherein the first bonding wires have one-end sides thereof connected tothe connecting portions and another-end sides thereof opposite to theone-end sides thereof connected to the first regions of the firstbonding pads, and wherein the second bonding wires have one-end sidesthereof connected to the second regions of the first bonding pads andanother-end sides thereof opposite to the one-end sides thereofconnected to the second bonding pads.
 25. The semiconductor deviceaccording to claim 24, wherein the first bonding wires are connected bya nail head bonding method which uses the connecting portions as a firstbond and the first bonding pads as a second bond, and wherein the secondbonding wires are connected by the nail head bonding method which usesthe first bonding pads as a first bond and the second bonding pads as asecond bond.
 26. The semiconductor device according to claim 24, whereinthe first bonding pads are formed in a rectangular shape, and whereinlong sides of the first bonding pads extend in a direction away fromsides of the semiconductor chip.
 27. The semiconductor device accordingto claim 20, wherein the first and the second bonding pads are formed ofpower source pads.
 28. The semiconductor device according to claim 20,wherein the semiconductor device further includes leads provided withthe connecting portions.
 29. The semiconductor device according to claim28, wherein the leads extend over the inside and the outside of thesealing body and project from side surfaces of the sealing body.
 30. Thesemiconductor device according to claim 28, wherein the sealing bodyincludes a main surface which is positioned at a side at which the mainsurface of the semiconductor chip is positioned and a back surface whichis positioned at a side opposite to the side of the main surface, andwherein the leads are exposed from a back surface of the sealing body.31. The semiconductor device according to claim 20, wherein thesemiconductor device includes a printed wiring circuit board on whichthe connecting portions are formed.
 32. The semiconductor deviceaccording to claim 20, wherein the semiconductor device furtherincludes: a printed wiring circuit board which mounts the connectingportions on a main surface thereof; and projection-like electrodes whichare electrically connected with the connecting portions and are arrangedat a back surface opposite to the main surface of the printed wiringcircuit board.
 33. A semiconductor device comprising: a semiconductorchip which has first, second and third bonding pads on a main surfacethereof, connecting portions which are arranged around the semiconductorchip; first bonding wires which electrically connect the first bondingpads of the semiconductor chip with the connecting portions; secondbonding wires which electrically connect the first bonding pads with thesecond bonding pads of the semiconductor chip; third bonding wires whichelectrically connect the second bonding pads with the third bonding padsof the semiconductor chip; and a sealing body which seals thesemiconductor chip, the connecting portions, the first, the second andthe third bonding wires.
 34. The semiconductor device according to claim33, wherein the first, the second and the third bonding pads arearranged along a first side of the semiconductor chip.
 35. Thesemiconductor device according to claim 33, wherein the first and thesecond bonding pads are arranged along the first side of thesemiconductor chip, and wherein the third bonding pads are arranged at asecond side of the semiconductor chip adjacent to the first side of thesemiconductor chip.
 36. The semiconductor device according to claim 33,wherein the second bonding wires are connected by a nail head bondingmethod which uses the first bonding pads as a first bond and the secondbonding pads as a second bond, wherein the third bonding wires areconnected by the nail head bonding method which uses the second bondingpads as a first bond and the third bonding pads as a second bond, andwherein one-end sides of the third bonding wires are connected to thesecond bonding pads via another-end sides of the second bonding wiresopposite to the one-end sides of the second bonding wires.
 37. Asemiconductor device comprising: a semiconductor chip having a mainsurface; a plurality of bonding pads which include a plurality of signalbonding pads which are formed on the main surface of the semiconductorchip and are arranged along a side of the semiconductor chip and firstand second power source bonding pads which are formed on the mainsurface of the semiconductor chip and are arranged to sandwich theplurality of signal bonding pads in plane and; a plurality of connectingportions which are arranged around the semiconductor chip and includepower source connecting portions and a plurality of signal connectingportions; a plurality of bonding wires which include first bonding wiresfor connecting the power source connecting portions with the first powersource bonding pads, second bonding wires for connecting the first powersource bonding pads with the second power source bonding pads and aplurality of third bonding wires for connecting the plurality of signalconnecting portions with the plurality of signal bonding pads; and asealing body which seals the semiconductor chip, the plurality ofconnecting portions and the plurality of bonding wires, wherein theconnection between the second bonding wires and the first power sourcebonding pads and the connection between the second bonding wires and thesecond power source bonding pads are performed at positions remoter froma side of the chip than the connection between the third bonding wiresand the signal bonding pads.
 38. A semiconductor device comprising: asemiconductor chip having a main surface; an internal circuit formingportion which is formed on the main surface of the semiconductor chip; aplurality of bonding pads which are formed on the main surface of thesemiconductor chip, are arranged between the internal circuit formingportion and sides of the semiconductor chip, and include first powersource bonding pads, second power source bonding pads and a plurality ofsignal bonding pads; third bonding pads which are formed on the mainsurface of the semiconductor chip and are arranged in the internalcircuit forming portion; a plurality of connecting portions which arearranged around the semiconductor chip and include power sourceconnecting portions and a plurality of signal connecting portions; aplurality of bonding wires which include first bonding wires forelectrically connecting the first power source bonding pads with thepower source connecting portions, second bonding wires for electricallyconnecting the first power source bonding pads with the third powersource bonding pads, third bonding wires for electrically connecting thesecond power source bonding pads with the third bonding pads and aplurality of fourth bonding wires for electrically connecting theplurality of signal bonding pads with the plurality of signal connectingportions; and a sealing body which seals the semiconductor chip, theplurality of bonding pads, the third bonding pads and the plurality ofconnecting portions.
 39. The semiconductor device according to claim 38,wherein a plurality of circuit blocks are arranged in the internalcircuit forming portion, and wherein the third power source bonding padsare arranged between the circuit blocks.
 40. The semiconductor deviceaccording to claim 38, wherein the plurality of connecting portions havea plurality of leads which are provided separately, and wherein theplurality of leads extend over the inside and the outside of the sealingbody and project from a side surface of the sealing body.
 41. Thesemiconductor device according to claim 38, wherein the plurality ofconnecting portions have a plurality of leads which are providedseparately, wherein the sealing body includes a main surface which ispositioned at a side at which the main surface of the semiconductor chipis positioned and a back surface which is positioned at a side oppositeto the main surface, and wherein the plurality of leads are exposed fromthe back surface of the sealing body.
 42. The semiconductor deviceaccording to claim 38, wherein the semiconductor device further includesa printed wiring circuit board provided with the connecting portions.